1. Field of the Invention
This invention relates to a logic verification device, a logic verification method and a logic verification computer program.
2. Description of the Related Art
In conventional operations of designing logic circuits by means of CAD techniques, the designed logic circuit is logically verified in order to eliminate logic design errors that can intervene during the design procedures by mistake.
If an error is detected as a result of logic verification, the designer looks into the cause of the error and corrects the designed logic circuit so as to remove the cause of the detected error.
Generally, the data to be processed in the operation of designing a logic circuit and correcting it (hereinafter referred to as real circuit data) and the data to be processed in the operation of logic verification (hereinafter referred to as data for verification) are different from each other in terms of data format. Therefore, the designer is forced to carry out the operation of designing a logic circuit, correcting it and logically verifying it repeatedly until no error is detected by logic verification, conducting data conversions between real circuit data and data for verification (see, inter alia, Patent Documents 1 through 3).
[Patent Document 1]
Japanese Patent Laid-Open No. 5-266134 (pp. 3–4, FIG. 1)
[Patent Document 2]
Japanese Patent Laid-Open No. 7-302281 (pp. 6–16, FIG. 1)
[Patent Document 3]
Japanese Patent Application Laid-Open Publication No. 2001-306646 (pp. 8–15, FIG. 1)
With conventional logic verification devices, when an error is detected at a spot in an area of the designed logic circuit as a result of logic verification, the process of logic verification is suspended at the time when the error is detected. In such an occasion, if another error exists at some other spot in the area where the error is detected (and hence a plurality of errors exist in the area that is subjected to logic verification), the second error is detected only when the logic is corrected at the spot where the first error is detected (e.g., circuit error 1 and circuit error 2 in the verification area between component a and component b of the circuit illustrated in FIG. 19).
In other words, when an operation of logic verification is conducted to follow the preceding operation of logic verification conducted on data for verification by converting the real circuit data obtained by the correction made to the spot where an error is detected in the real circuit data during the preceding operation of logic verification into data for verification, another error can be detected at some other spot regardless of the correction. If such is the case, the operation of converting real circuit data into data for verification and vice versa needs to be repeated for a number of times in order to detect a plurality of errors in an area selected for logic verification. This is a cause, among others, of a large number of steps that are involved in designing a logic circuit.
Additionally, since it is impossible to locate the errors other than the currently detected error that may exist, a correction technique that may not be the best one may inevitably be applied to the operation of correcting the detected error. Consequently, the previously applied correction technique may have to be altered when some other error is detected. Such an alteration to the previously applied correction technique entails an unnecessary operation of converting real circuit data into data for verification and vice versa and an increased number of steps that are involved in designing a logic circuit.